March 19, 1999

Overview

Version 1.8.0 of the V6M6 software and FPGA configurations includes the following changes:

• Hardware and software modifications for DM12C549 DSP modules.

• Software modifications for DM4C51 DSP modules.

• Hardware modifications for PM4700A MIPS modules.

• Modification to the handling of VME to PCI access retries and timeouts.

• Modifications to the V6M6 micro-controller program.

• Modifications to various support and diagnostic programs.

• New diagnostic to test host DMA data transfers.

• Preliminary support for new IM4SER modules.

• Other modifications to the V6M6 host library.

• Special options for global timing signals.

Note: This release includes new flash files for FPGA configurations. Be sure to run pciflashup after installing the software.

Hardware and Software Changes for DM12C549 DSP Modules

New functionality in the DM12C549 hardware configuration include:
- Delayed data transfers with queuing
- Burst mode data transfers with prefetching
- DMA data transfers between DSPs and the PCI bus
- Fixes for problems with HPI access during PLL stabilization period
   and DSP reset being de-asserted during HPI access.

Some of these features required changes in the PCI bus address mapping for the DM12C549 module and corresponding modifications to the host library functions and the pciinit program. These changes are neither forward or backward compatible with each other. To use the new host software (from Release 1.8.0 or above) the DM12C549 configuration data must be updated in the V6M6 flash to at least version 9 (dm12c5499.mcs). Modules configured with the new configuration data (version 9 or above) must be used with the new software version (from Release 1.8.0 or above).

DMA data transfer capability and handling of the PLL stabilization problem also required changes to files dm12c549.h and boot.asm used for compiling C549 code. These are located in the $CAC/pci/modsupport/dm12c549 directory.

The dm12c549_hostimask library function is fixed to only enable the VME interrupt mask when an interrupt on the module is being enabled. The previous version would enable the VME interrupt mask if other interrupt mask bits had been left enabled on the same module.

It was discovered that the C549's ROM boot loaded code sets interrupt status whenever the DSP's reset signal is de-asserted. Clearing of this interrupt status is now done in the dm12c549_init and dm12c549_run functions so that there is no longer an interrupt left pending after initialization or program execution is started.

The dm12c549_init function now includes the DSP's V6M6 module ID in the value stored at the DSPMODID memory location (0x17f8). The value stored in this location now consists of the DSP ID (0 through 11) in bits 3:0 and the module ID (0 through 5) in bits 10:8. Code is also added to the dm12c549_init function to clear the EMPID memory location (0x17f6) so DSP programs can determine whether they are running on a V6M6 or EmPack platform.

Software Changes for DM4C51 DSP Modules

The dm4c51_hostimask library function is fixed to only enable the VME interrupt mask when an interrupt on the module is being enabled. The previous version would enable the VME interrupt mask if other interrupt mask bits had been left enabled on the same module.

Code is added to the dm4c51_run function to clear the EMPID memory location (0x1ff6a) so DSP programs can determine whether they are running on a V6M6 or EmPack platform.

Hardware Changes for PM4700A MIPS Modules

The PM4700A FPGA configuration is modified so that PCI master cycles will continue when the GNT signal is de-asserted. This is required for PCI burst operations to or from DM12C549 modules.

Clearing burst error status now uses bit 26 instead of bit 24 in the PCI AD register to be consistent with the PM4600 and PM4700 modules.

Handling of VME to PCI Access Timeouts and Retries.

Two issues concerning PCI transactions initiated from the VME bus are addressed in this release.

The first issue involves the host library's software timeout when waiting for a data transfer to complete. The combination of a very busy PCI bus (as exhibited by the pcimemslice diagnostic program) and a fast host processor with a fast VME interface can increase the ratio of PCI latency to status polling time beyond what was originally expected. To account for this, the maximum number of status register polls is increased by a factor of 5.

The second issue involves the handling of PCI bus retries in the VME/PCI interface logic. Changes in the DM12C549 module's PCI interface result in an increased average number of retries from DM12C549 modules. The VME/PCI interface would abandon a transaction after a fixed number of PCI retries. The new version of the VME/PCI interface for version 2 or 3 V6M6 boards replaces the fixed retry count with a timeout-based mechanism. This provides a more reliable means of gauging bus latency and error handling.

Modifications to the V6M6 Micro-controller Program

The micro-controller program is modified to properly initialize the frequency synthesizer on DM12C549 modules, to provide additional FPGA configuration clocks required for the IM4SER module, and to support modifications to the VME/PCI Interface FPGA on version 3 V6M6 boards (vmepcic114 and higher).

Support and Diagnostic Program Modifications

The new Support and Diagnostic Programs section of the V6M6 reference manual describes details and usage of the V6M6 support and diagnostic programs.

The pciinit program is modified for the new addressing modes on DM12C549 modules and to provide initialization of IM4SER modules. It also includes the new -k and -K options to set a special mode on the boards described below.

The pciflashup program is fixed to correctly recognize module types that have standard PCI interface components but still require FPGA configuration data to be stored in the V6M6 flash. It is also modified to clear the special mode in VME/PCI interface described below.

The pcidmexec program now supports DM12C549 modules.

The pcichip diagnostic now includes code to ensure that all processors are halted in case errors occur while the program is still initializing other processors on the board.

The pcimemory diagnostic is now supported under VxWorks. It now supports new access modes on DM12C549 modules. Its status display includes additional information to indicated the total number of tests run besides the number of complete iterations.

The pcimemslice diagnostic now supports DM12C549 modules as memory targets from other PCI modules and the host. Support for DM12C549 modules as PCI bus masters will be included in a future release.

The pcinicstar diagnostic for IMATM modules now uses circular buffers for multiple or continuous message transfers and sets the TDM frame rate to 8 kHz to properly synchronize the module's PLL. The default data rate is changed from 55 MHz to 51 MHz. It has a new -S option to run only the SRAM test. Additional commands in "debug" mode allow for reading the module's PCI configuration registers.

The pcitdm diagnositc's TDM mapping is changed to for better operation with DM12C549 modules.

The pcifft and pciscp diagnostics are modified to display an error message if an unsupported sampling rate is specified rather than just displaying the usage message.

The pciscsa diagnostic now multiplies the number of messages specified with the -M option by 1,000,000 instead of 1,048,576.

The pcig726 diagnostic handles errors in command line options better.

The pcihdlc diagnostic is fixed to display error and status information properly after being interrupted.

The pciburn program now runs the pcinicstar diagnostic with options to transfer 400 message bursts by default. The -i option is added to allow the global test cycle time to be specified.

New Diagnostic to Test Host DMA Transfers

A new diagnostic program, pcihostdma, is now available to test host-initiated DMA transfers with V6M6 boards. This data transfer capability is currently supported on the following host platforms:
- Force Sparc CPUs running Solaris 2.5 or higher
- Force PowerCore 604 CPUs running VxWorks 5.3.1 or higher

The program tests transferring data to and from a V6M6 with modes for comparing the data, measuring the over-all transfer times, and debugging problems. The Support and Diagnostic Programs manual describes the program's usage.

Preliminary Support for IM4SER Modules

The IM4SER mini-PCI module provides 4 high-speed serial ports for V6M6 applications. This version of the V6M6 software release provides the basic infrastructure for recognizing and supporting these modules.

Other Modifications to the V6M6 Host Library

The "Makefile" in the libsrc directory is modified to add the -D_REENTRANT option to the compiler flags. This provides proper handling of the global variable, errno, for multi-threaded applications.

A new function, pci_tdm_freq, is available to determine the reference frequency that is used to generate TDM clocks on the V6M6 baseboard. The nominal frequency is 16.384 MHz.

    double
    pci_tdm_freq(PCI_TDM *tdm)

Passed an open PCI_TDM handle, it returns the actual reference frequency, in MHz, that is generated by the board's frequency synthesizer. In normal circumstances, the reference frequency will be within 62 parts per million. However, if the frequency has been programmed to some unusual rate, the value returned may be used to determine any required adjustment in the number of slots per TDM frame to achieve a specific TDM frame rate.

The pci_tdm_timing function is fixed so that when it modifies the TDM clock driver setting on IMATM modules it does not modify any other control bits in the NicStar chip's General Purpose register.

The COFF file reading code is modified to handle different sizes of s_flag tokens as required for code generated by TI DSP compilers.

Special Options for Global Timing Signals

A specific application requires a global timing signal to be delivered across the VME backplane to V6M6 boards. In lieu of having to add wires to each V6M6 board, a special mode was designed into the VME/PCI interface and TDM control logic to route a signal from the Bus Grant Out signal on the VME backplane to the TDM superframe signal on each board. Using this mode diables the normal use of the VME Bus Grant daisy chain for the Bus Grant level selected in the V6M6 device driver options. It also disables the V6M6 VME/PCI interface from responding to PCI memory cycles and becoming a VME bus master.

The V6M6 boards are set into this mode using the -k and -K options to the pciinit program. See the description of pciinit in the Support and Diagnostic Programs Manual for details. This mode also uses one of the JTAG signals on the board and, therefore, the pciflashup program is modified to force the boards out of this mode to enable proper configuration of FPGAs on the board.