February 12, 2009

Overview

The following changes are introduced in this release:

• Fix for interrupts on DPT5 boards.

• Updates to some diagnostic programs.

• An interrupt test mode is added to the Linux and Solaris device drivers.

• Component versions for this release.

• Known problems.

Notes:

This release includes a new FPGA configuration for DPT5 and DPT6 boards. Run the dpflashup program after installation to update the FPGA configuration on DPT5 and DPT6 boards.

Fix for Interrupts on DPT5 Boards

The new FPGA configuration for DPT5 and DPT6 boards includes a fix for the interrupt signal on DPT5 boards. Without this fix the interrupt signal can cause contention with interrupts on other boards connected to the same PCI bus. (The problem was introduced in version 1.5.5 of the FPGA with changes to resolve interrupt problems for DPT6 boards.)

Updates to Some Diagnostic Programs

The dpdmaxfer program is fixed to report that errors occurred in the case that a DMA transfer operation fails as well as for data corruption errors.

The dpchantest program has a new -w argument for tracking "high-water" debug values for DMA transfers. These are only available for DPT5 and DPT6 boards and only with newer FPGA configurations.

A -w option is also added to the dpdiag and dpburn programs which then enable the option for the dpchantest portion of the tests. These programs are modified in the way they display and log additional messages form the test programs they run.

A new command, "openx", is added to the dpdebug program for opening a board with exclusive access. The program is also modified to not retry device opens if the initial attempt fails due to the device entry not existing or the device is busy.

An Interrupt Test Mode is Added to the Linux and Solaris Device Drivers

A special test mode for interrupts is added for the Linux and Solaris device drivers. When enabled, with the use of a special ioctl request, the interrupts for embedded processor message and channel DMA activity are handled by sending software signals to a host process instead of the normal servicing mechanism. Currently this is only used by manufacturer (CAC) debugging programs.

Component Versions for This Release

The DPT software release includes several components of software, embedded code and hardware FPGA configurations. The major and minor version numbers are the same within each category. However the update version number of each component may vary depending on the number of changes and iterations each component has gone through between releases.

The components and their versions for DPT Software Release 1.5.4 are:

Software Components		Version
	API Library and Programs	1.5.4
	Solaris Device Driver	1.5.4
	Linux Device Driver	1.5.4
	Windows Device Driver	1.5.1
Embedded Code Components
	Embedded MIPS Loader	1.4.0
	Embedded MIPS Application	1.4.10
DPT4 Hardware Components
	PLD Configuration	1.4.0
	Host FPGA Configuration	1.4.5
	Expansion FPGA Configuration	1.4.1
DPT5 & DPT6 Hardware Components
	PLD Configuration	1.5.1
	FPGA Configuration	1.5.8

Known Problems

The following problems are known to exist in this release:
• The data buffers in the dual-port memory can overflow as channels are being started. The overflow can corrupt data for a channel whose buffer is using an adjacent area of the dual-port memory. The problem only occurs when a channel is being started and only occurs on DPT4 boards, not DPT5 or DPT6 boards.

  A suitable work-around for applications that open all their channels at start-up is to wait for all channels to be opened and then flush receive channels before using received data.

• Large amounts of channel data being written to the transmit buffers can saturate the board's local bus, preventing the MIPS processor from obtaining access to the board's local bus long enough to miss buffer interrupts. This has been known to cause corruption of transmitted data and timeout errors reported by the dpchantest diagnostic program. The problem mostly appears on fast systems that are capable of downloading data fast enough to cause the local bus to saturate.

  The only work-around at this time is for applications to limit the rate at which they write data to transmit channels. The suggested limit is an aggregate download rate to approximately 24 Mbytes per second or, assuming all E1 channels are being used,

• Switching to non-blocking I/O mode using the pci_chan_blocking function does not work in all cases for channels that are initially opened with blocking mode. The issue may be dependent on the host operating system as well as other factors. The pci_chan_blocking appears to be able to switch back and forth for channels opened initially with non-blocking mode.

• On rare occasions, DPT5 and DPT6 boards have been known fail to complete a channel DMA transfer. To date, this issue has only been seen on some older desktop systems when multiple boards are running our burn-in tests. A method for detecting possible causes have been added to the FPGA and diagnostic programs.

• On rare occasions a DPT4 board can hang during the initialization process. This has only been known to occur when being initialized the first time following a power cycle.