New features implemented include:

• access to the SDRAM from both PCI bus and the DSPs.
• interrupts to the DSPs in the event of PCI bus access errors.
• enhancements to the design for compatibility with V6M6HS base boards.
• support for the modules in the various memory and chip diagnostic programs.
• support for the modules in the DSP frequency setting utility (dmfreq).

The host application library and diagnostic programs have been updated to recognize the new module type and test its additional memory.

This software release includes modifications to programs and sections of the host application library required to accommodate the new flash memory.

    PCI_MOD *c549_broadcast;

    c549_broadcast = dm12c549_open("pci0a12");

This provides simultaneous write operations, using the dm12c549_dl_* functions, to all 12 of the DSPs on the module. Uploads from this resource, using the dm12c549_up_* functions, will read data from DSP0 on the module.

• decoding of local bus address bit 32 to interpret the access as a PCI Memory Space address.
• a logic change to avoid local bus hang if the processor reset is asserted during a cache fill error.

• access to the SDRAM from both PCI bus and the DSPs.
• access to TDM control and data lines via the DSPs' McBSP ports for diagnostic purposes.
• a special "DMA Shared Queue" method for DSP to PCI bus DMA transfers.

The P2CI interface logic (p2ci14.mcs) is modified to add P2CI to Local PCI bus functionality, increase the P2CI BAR to 1 GB, increase the SDRAM BAR to 64 MB and a special address aliasing mode for ATM SCQ tables.