pcifreq

Sets the frequencies of the PCI bus clock and the TDM subsystem base rate clock.

Sets the local bus and processor clock frequency on PM4700A and PM5000 MIPS modules.

Sets the local bus and processor clock frequency on DM2C31 and DM4C51 DSP modules.

These programs are compiled into a new VxWorks object file named pciutil.o. It may be loaded separately or with the entire V6M6 software library which is named pciall.o.

VxWorks sometimes sets the global variable, errno, to a value with additional high-order bits turned on. The upper parts of the value are now masked out in the V6M6 implementation of the perror function when it uses the value to index the array of error strings.

pciinit

The software delay after a hardware reset has been decreased when boards are set into low-power mode.

pciinfo

Module types are determined from data in the modules' EEROMs. This allows some information to be displayed in cases where pciinit has not been run prior to using pciinfo. A rudimentary screen-pager has been added to avoid information scrolling off the screen. It is invoked only if the -p option is used.

pmfreq and dmfreq

These utilities for adjusting the clock frequencies on PM4700A, PM5000, DM2C31 and DM4C51 modules now obtain module type information for the EEROM on the modules. This allows these utilities to be used without pciinit having been run first.

DM4C51 Modules

New version 27 of the FPGA configuration for DM4C51 modules removes the extra delay between the TDM frame boundary and updating the TDM buffer pointer. The extra delay was inadvertently added when the fixes for SC4000 routing data corruption were implemented in version 22 of the DM4C51 configuration. The delay was not noticeable when C language interrupt handlers were used. However, optimized interrupt entry code written in assembler language might read the buffer pointer before it was updated by the hardware.

PM4700A and PM5000 Modules

Version 6 of the PM4700A and PM5000 modules fixes a problem with handling LDR and LDL instructions for non-aligned accesses to local or PCI bus memory.

VME-PCI Interface (V6M6 Rev 2)

Version b111 of the FPGA configuration for the VME-PCI interface logic on revision 2 V6M6 baseboards fixes marginal timing when the PCI bus clock frequency is set higher than 20 MHz.