New DM4C51 Module Subtypes
The following module types for the DM4C51 are now supported:
PCI_DM4C51
This is the standard DM4C51 module with
128K of external memory partitioned as
64K for program and 64K for data.
PCI_DM4C51_JTAG
A DMC451 module with a JTAG header installed for program debugging.
PCI_DM4C51_64K
A DM4C51 module with 64K of external unified memory
(program and data reside in a single memory segment).
PCI_DM4C41_64K_JTAG
A DMC451 module with 64K of unified memory
and JTAG header installedfor program debugging.
Note that for the 64K modules, memory address bit 16 is pulled up
so when linking your code, both program and data must be placed in SRAM1 bank.
This does not effect the C51 memory address since it can only address
64K external, but is used by the host library to determine which bank of
memory to load and resolve address labels properly.
Data space must account for the first 0x800 words reserved by the C51.
Below is an example of a 128K linker file for the C51:
/****************************************************************/
/* TI C51 linker command file for DSP Module 4 C51 Board (128K) */
/****************************************************************/
-c /* Link using C Conventions */
-v0 /* Generate Version 0 COFF format */
-w /* Generate Warnings */
-stack 0x100 /* 256 Stack */
-heap 0x2002 /* 8194 Heap - Size to allocate */
/* one 4095 dma buffer */
-lc51int00.obj /* must be before run-time lib. */
-lrts50.lib /* Run-time Support */
MEMORY
{
PAGE 0: VECT: o = 0x0000, l = 0x30 /* Interrupt Vectors */
SRAM0: o = 0x0030, l = 0xffd0 /* 64K words */
PAGE 1: SRAM1: o = 0x10800, l = 0xf660 /* 64K words */
STACK: o = 0x1fe60, l = 0x0100 /* Stack Space */
}
SECTIONS
{
vectors: {c51int00.obj(.vect)} > VECT PAGE 0 /* Vector Table */
.boot: {c51int00.obj(.text)} > SRAM0 PAGE 0 /* Startup code in mem */
.cinit: > SRAM0 PAGE 0 /* Initialization Tables */
.text: > SRAM0 PAGE 0
.switch: > SRAM0 PAGE 0 /* Switch Statement Tables */
.data: > SRAM0 PAGE 0 /* Assembly Language Const */
.const: > SRAM1 PAGE 1 /* Constants */
.bss: > SRAM1 PAGE 1, block = 0x80, fill = 0
.sysmem: > SRAM1 PAGE 1 /* Dynamic Memory */
.stack: > STACK PAGE 1 /* System Stack */
}
Below is an example of a 64K linker file for the C51:
/******************************************************************/
/* TI C51 linker command file for DSP Module 4 C51 Board (64K) */
/* configurated with a 64 Kword unified Program/Data Memory Space */
/******************************************************************/
-c /* Link using C Conventions */
-v0 /* Generate Version 0 COFF format */
-w /* Generate Warnings */
-stack 0x100 /* 256 Stack */
-heap 0x2002 /* 8194 Heap - Size to allocate */
/* one 4095 dma buffer */
-lc51int00.obj /* must be before run-time lib. */
-lrts50.lib /* Run-time Support */
MEMORY
{
PAGE 0: VECT: o = 0x10000, l = 0x30 /* Interrupt Vectors */
SRAM1: o = 0x10800, l = 0xf660 /* 64K words */
STACK: o = 0x1fe60, l = 0x0100 /* Stack Space */
}
SECTIONS
{
vectors: {c51int00.obj(.vect)} > VECT PAGE 0 /* Vector Table */
.boot: {c51int00.obj(.text)} > SRAM1 PAGE 0 /* Startup code in mem */
.cinit: > SRAM1 PAGE 0 /* Initialization Tables */
.text: > SRAM1 PAGE 0
.switch: > SRAM1 PAGE 0 /* Switch Statement Tables */
.data: > SRAM1 PAGE 0 /* Assembly Language Const */
.const: > SRAM1 PAGE 0 /* Constants */
.bss: > SRAM1 PAGE 0, block = 0x80, fill = 0
.sysmem: > SRAM1 PAGE 0 /* Dynamic Memory */
.stack: > STACK PAGE 0 /* System Stack */
}